RISC-V has gone from academic experiment to enterprise silicon — what the open-source ISA means for the chip industry

In 2010, a team at UC Berkeley set out to design an instruction set architecture they could use in academic research without navigating the licensing complexities of ARM or x86. The result was RISC-V — pronounced "risk five" — a clean, minimal ISA released into the public domain. Sixteen years later, RISC-V International has over 4,000 member organizations, the architecture is ratified for everything from embedded microcontrollers to high-performance computing, and it has become a focal point in the geopolitics of semiconductor independence.

What RISC-V actually is

An ISA defines the interface between hardware and software: the set of instructions a processor understands, the register layout, the memory model. Intel's x86 and ARM Holdings' ARM are the dominant ISAs for servers/PCs and mobile/embedded respectively. Both are proprietary. Using ARM requires a license from ARM Holdings; that license costs money and comes with usage restrictions. RISC-V has no owner. Anyone can implement it, modify it, and ship products based on it without paying royalties or seeking permission.

RISC-V is not a chip. It's a specification — a document describing what instructions a processor must support. The base integer instruction set (RV32I or RV64I for 32-bit and 64-bit respectively) is intentionally minimal. Extensions add floating point (F, D), atomic operations (A), compressed instructions (C), vector processing (V), and more. A processor that implements RV64GC — the most common configuration for application processors — supports the base set plus general-purpose extensions and compressed instructions.

Where RISC-V already runs

The deployment picture is broader than most people realize. Espressif's ESP32-C3, a WiFi and Bluetooth chip used in countless IoT devices and consumer electronics, runs a single-core RISC-V processor. The chip costs roughly $1 in volume and ships in hundreds of millions of units annually. Western Digital uses custom RISC-V cores in the controllers of its SSDs and hard drives — a deployment of well over a billion cores. NVIDIA's GPU microcontrollers transitioned from proprietary Falcon cores to RISC-V starting with Turing-generation cards in 2018.

Google added RISC-V as a supported ABI in Android 13 in late 2023, the first step toward Android running on RISC-V application processors. The Linux kernel has supported RISC-V in mainline since 2017. GCC, LLVM/Clang, and Rust all have mature RISC-V targets. The toolchain ecosystem, which was the weakest point five years ago, has matured substantially.

For more capable silicon, SiFive — a US startup that creates commercial RISC-V cores — has produced the P870 and X280 families targeting edge computing and eventually entry-level server workloads. Alibaba's T-Head division open-sourced its XuanTie C910 core in 2021, a high-performance 64-bit RISC-V implementation that Alibaba uses internally and licenses externally. Several RISC-V single-board computers — the StarFive VisionFive 2, the Milk-V Pioneer — now run full Linux desktop environments.

The geopolitical accelerant

RISC-V's adoption curve steepened sharply after 2020, when US export controls began restricting semiconductor technology exports to China. ARM Holdings, a UK company but with US-designed technology in its cores, faced uncertainty about whether its licenses to Chinese companies could continue. Huawei, in particular, accelerated investment in RISC-V alternatives after the US effectively blocked it from using ARM's most advanced cores.

China now represents a significant fraction of global RISC-V development activity. Alibaba's T-Head, ISCAS (Institute of Computing Technology at the Chinese Academy of Sciences), StarFive, and dozens of smaller companies are shipping RISC-V silicon. The Chinese government has included RISC-V development in its semiconductor self-sufficiency plans. RISC-V's open nature means US export controls cannot block access to the ISA specification itself — only to specific implementations or toolchain components from US companies.

This has created an interesting dynamic: RISC-V International, which governs the specification, has members from both the US and China. The specification is developed collaboratively. The competitive implementations are separate.

The vector extension and AI workloads

The RISC-V V (vector) extension was ratified in 2021 and is now supported in hardware by several processors including the T-Head C910 and SiFive's X280. Vector processing enables SIMD-style parallelism for operations like matrix multiplication — the core computation in neural network inference. This makes RISC-V relevant for edge AI accelerators, which are a major growth market.

Several startups are building AI inference chips based on RISC-V vector cores specifically because the open ISA gives them complete control over the instruction mix without licensing constraints. For custom silicon designed for a specific model architecture, this flexibility matters.

Where the gaps remain

Servers and laptops are the two markets where RISC-V has not yet demonstrated competitive performance at scale. The fastest RISC-V application processors in 2026 are broadly comparable to mid-range ARM Cortex-A55 parts from several years ago — adequate for embedded and entry-level edge work, not competitive with Apple Silicon, AMD Zen 5, or even the ARM Cortex-X4. The gap exists partly because ARM and x86 processors benefit from decades of microarchitectural optimization, enormous R&D budgets, and manufacturing at the most advanced process nodes.

Ecosystem fragmentation is a structural concern. RISC-V's extensibility — the feature that makes it flexible — also means different chips can implement different extensions, making it harder to write software that runs well everywhere. ARM solved this by keeping tight control over its profiles; RISC-V's openness means there's more variation in what "RISC-V" means in practice.

The RISC-V Software Ecosystem (RISE) project, launched in 2023 with backing from Google, Intel, Qualcomm, and others, is working to coordinate software stack development and prevent fragmentation. How effective this proves to be will significantly affect whether RISC-V can move into higher-performance markets or remains strong primarily in embedded and IoT applications where compatibility requirements are narrower.

The trajectory is clearly upward. RISC-V is not displacing ARM or x86 in the near term — those architectures have too much performance headroom, ecosystem depth, and manufacturing investment. What it is doing is carving out a large and growing space in the embedded, IoT, and edge markets while building the ecosystem prerequisites for a future push into higher-performance computing. The chip industry is watching.