Silicon Photonics: How Light Is Solving AI's Compute and Energy Crisis

A single NVIDIA H100 GPU draws 700 watts. A large AI training cluster running 100,000 of them consumes more power than a medium-sized city. AI datacenters' electricity use is projected to grow 160% by 2030, reaching nearly 945 terawatt-hours annually — roughly equivalent to Japan's total electricity consumption. Local governments are blocking new datacenter permits. Power utilities are struggling to provision capacity fast enough. The AI industry has an energy problem, and the chips themselves are only part of it.

A significant and underappreciated share of that energy — up to 50% in densely packed clusters — is consumed not by computation, but by moving data between chips. The copper electrical interconnects that link GPUs to each other and to memory heat up, resist high data rates, and dissipate enormous amounts of energy as heat. The physics of copper at scale is a wall that traditional approaches cannot move.

Silicon photonics is the field that proposes replacing those copper interconnects with light. The core idea is using optical signals — pulses of laser light traveling through silicon waveguides — to carry data between chips and across racks. Light travels without electrical resistance, without generating heat from signal transmission, and at bandwidths that copper wires cannot match. In 2026, the technology is making a transition from promising research to volume production, and the numbers are significant enough to matter for the industry's energy trajectory.

How it works

Silicon photonics builds optical components — waveguides, modulators, photodetectors — onto silicon chips using the same CMOS manufacturing processes already used for processors. This matters because it means optical components can be fabricated at scale in existing semiconductor foundries rather than requiring entirely new manufacturing infrastructure. Intel has been manufacturing silicon photonic transceivers this way since the mid-2010s; the technology has been commercially proven for datacenter interconnects for nearly a decade.

The efficiency gains come from the physics of light versus electrons. Optical signals consume as little as 0.05 to 0.2 picojoules per bit transmitted, versus much higher figures for copper over comparable distances. Co-Packaged Optics — integrating optical engines directly into the chip package rather than using pluggable modules at the rack edge — reduces interconnect power by approximately 75% compared to current pluggable optical solutions, and by an estimated 70% compared to equivalent electrical alternatives.

The companies building it

Three startups are leading the commercial push into AI-scale silicon photonics, each with a different technical approach.

Lightmatter's Passage platform centres on photonic interposers — essentially optical circuit boards that sit between chips, connecting them with light rather than copper traces. The Passage M1000, available since summer 2025, achieves 114 terabits per second of total optical bandwidth across a 4,000 square millimetre photonic interposer. The Passage L200X, targeting production in 2026, delivers 64 Tbps per package for next-generation AI accelerators and switches. Lightmatter built on GlobalFoundries' GF Fotonix silicon photonics platform, giving it a manufacturing partner with the scale to move beyond pilot production.

Ayar Labs took the chiplet route. Its TeraPHY, the world's first UCIe-standard optical I/O chiplet, integrates an 8 Tbps optical interface directly into an AI chip's package using TSMC's advanced 3D packaging. The third-generation TeraPHY, launched in early 2025, claims 5 to 10 times more bandwidth than copper alternatives, 10 times lower latency, and 3 to 5 times better power efficiency. In September 2025, Ayar announced partnerships with Alchip Technologies and Global Unichip Corp to bring co-packaged optics into production chip designs via TSMC's COUPE packaging technology.

Celestial AI, acquired by Marvell in December 2025 for $3.25 billion, pursued the most aggressive integration: embedding optical interconnects directly into the silicon die itself rather than as a separate layer. Its Photonic Fabric chiplet delivers 16 Tbps bandwidth per chiplet, and the full module — combining a TSMC 5nm ASIC with photonic interposer and HBM3e memory stacks — provides 7.2 Tbps of optical connectivity. Marvell's acquisition is expected to accelerate scale deployment, with revenue contributions projected from late 2027.

The hyperscalers are already buying

The most significant signal for silicon photonics' near-term trajectory is not the startups — it is the procurement decisions of hyperscalers. Microsoft has deployed silicon photonic interconnects in Azure datacenters since 2016, and in November 2025 deepened integration across its AI cluster infrastructure. Google enhanced its internal deployment of optical circuit switching and photonic interconnects in December 2025. AWS, Google, Meta, and Microsoft have all committed to co-packaged optics in next-generation network upgrades, with active procurement programs running in 2025 and 2026.

The volume numbers reflect this momentum. The 1.6 terabit-per-second optical module — the current leading-edge product — is projected to scale from roughly 2.5 million units shipped in 2025 to 20 million units in 2026. Silicon photonics is expected to capture 50 to 70% of this high-bandwidth segment by year-end. The datacenter photonics market overall is forecast at $2.7 billion in 2026, growing to $4.1 billion by 2034.

What remains hard

The remaining challenges are real and worth naming. Laser integration is the most fundamental: silicon does not emit light naturally because of its electronic structure, so practical silicon photonics requires bonding light-emitting materials (typically indium phosphide) onto silicon substrates. The manufacturing precision required is significant, and complex photonic integrated circuits currently yield below 60% for advanced designs.

Thermal sensitivity is a persistent headache. The ring resonators and interferometers that form the core optical components of silicon photonic chips are extremely sensitive to temperature variations — a few degrees can detune them enough to cause signal errors. Active thermal tuning and stabilization add complexity and power overhead that partially offset the efficiency gains.

The supply chain is also concentrated in ways that create risk. TSMC is currently the only foundry capable of the ultra-precise 3D chip stacking required for co-packaged optics at scale. Any disruption to TSMC's production would cascade across the entire photonics supply chain for AI.

The trajectory

The arc of silicon photonics in AI infrastructure is clearer now than it has been at any previous point. Hyperscalers are not piloting the technology — they are procuring it at scale. The leading startups have graduated from demos to shipping products. Volume production of 1.6T modules is underway. Intel's silicon photonics share in optical transceivers is at roughly 30% today, forecast at 60% by 2030.

The copper wall that constrains today's AI clusters is a real physical limit, not a planning problem that more funding can solve. Silicon photonics is the clearest path around it. Whether the transition happens fast enough to change the energy trajectory of AI infrastructure is a question of manufacturing scale and supply chain development more than fundamental technology. In 2026, the evidence suggests it is happening faster than most observers expected.